Via is one of the important components of multi-layer PCB, and the cost of drilling holes usually accounts for 30% to 40% of the PCB manufacturing cost. Simply put, every hole on a PCB can be called a via. From a functional perspective, vias can be divided into two categories: one is used for electrical connections between layers; The second is used for fixing or positioning devices. If we look at the manufacturing process, these vias are generally divided into three categories: blind via, buried via, and through via. Blind holes are located on the top and bottom surfaces of printed circuit boards, with a certain depth, used for connecting surface circuits and underlying inner circuits. The depth of the holes usually does not exceed a certain ratio (aperture). Buried hole refers to the connection hole located in the inner layer of the printed circuit board, which does not extend to the surface of the circuit board. The above two types of holes are located in the inner layer of the circuit board and are completed using through-hole forming technology before lamination. During the through-hole formation process, several inner layers may overlap and be made. The third type is called a through-hole, which passes through the entire circuit board and can be used for internal interconnection or as a mounting and positioning hole for components. Due to its easier implementation and lower cost in the manufacturing process, most printed circuit boards use through-hole instead of the other two types. The vias mentioned below, unless otherwise specified, are considered as through holes. From a design perspective, a via mainly consists of two parts: a drill hole in the middle and a pad area around the drill hole. The size of these two parts determines the size of the via hole. Obviously, in high-speed and high-density PCB design, designers always hope that the smaller the via, the better, so that there can be more wiring space on the board. In addition, the smaller the via, the smaller its own parasitic capacitance, making it more suitable for high-speed circuits. However, the reduction in hole size also brings about an increase in cost, and the size of through holes cannot be reduced without restrictions. It is limited by processes such as drilling and plating: the smaller the hole, the longer it takes to drill and the easier it is to deviate from the center position; And when the depth of the hole exceeds 6 times the diameter of the borehole, it cannot be guaranteed that the hole wall can be uniformly plated with copper. For example, if the thickness (through-hole depth) of a normal 6-layer PCB board is 50mil, then under normal conditions, the drilling diameter that PCB manufacturers can provide can only reach 8Mil. With the development of laser drilling technology, the size of boreholes can also become smaller and smaller. Generally, through holes with a diameter of less than or equal to 6Mils are called micropores. Micro holes are often used in HDI (high-density interconnect structure) design, and micro hole technology allows vias to be directly drilled on the via in pad, greatly improving circuit performance and saving wiring space.

Vias on transmission lines appear as discontinuities in impedance, which can cause signal reflection. The equivalent impedance of a typical via is about 12% lower than that of a transmission line. For example, a 50 ohm transmission line will experience a 6 ohm decrease in impedance when passing through a via (depending on the size of the via and the thickness of the board, not the decrease). However, the reflection caused by impedance discontinuity in via holes is actually negligible, with a reflection coefficient of only (44-50)/(44+50)=0.06. The problems caused by via holes are more concentrated on the influence of parasitic capacitance and inductance. 2、 The parasitic capacitance of vias and inductive vias themselves have parasitic stray capacitance. If the diameter of the solder mask on the ground layer of the via is D2, the diameter of the via pad is D1, the thickness of the PCB board is T, and the dielectric constant of the substrate is ε, then the parasitic capacitance of the via is approximately C=1.41 ε TD1/(D2-D1). The parasitic capacitance of the via will mainly affect the circuit by prolonging the rise time of the signal and reducing the speed of the circuit. For example, for a PCB board with a thickness of 50mil, if the diameter of the via pad used is 20Mil (drilling diameter is 10Mils) and the diameter of the solder mask is 40Mil, we can approximately calculate the parasitic capacitance of the via through the above formula as C=1.41x4.4x0.050x0.020/(0.040-0.020)=0.31pF. The change in rise time caused by this capacitance is approximately T10-90=2.2C (Z0/2)=2.2x0.31x (50/2)=17.05ps. From these values, it can be seen that although the effect of the parasitic capacitance of a single via on the rise delay is not very obvious, if multiple uses are made in the wiring, When switching between layers, multiple through holes will be used, and careful consideration should be given during design. In practical design, parasitic capacitance can be reduced by increasing the distance between via holes and copper plated areas (Anti pad) or reducing the diameter of solder pads. In the design of high-speed digital circuits, the parasitic inductance of via holes often poses greater harm than the impact of parasitic capacitance, as there are both parasitic capacitance and parasitic inductance present in via holes. Its parasitic series inductance will weaken the contribution of bypass capacitors and weaken the filtering effectiveness of the entire power system. We can use the following empirical formula to simply calculate the parasitic inductance of a via approximation: L=5.08h [ln (4h/d)+1], where L refers to the inductance of the via, h is the length of the via, and d is the diameter of the central borehole. From the equation, it can be seen that the diameter of the via has a relatively small impact on the inductance, while the length of the via affects the inductance. Still using the above example, the inductance of the via can be calculated as L=5.08x0.050 [ln (4x0.050/0.010)+1]=1.015nH. If the rise time of the signal is 1ns, then its equivalent impedance size is XL=π L/T10-90=3.19 Ω. This impedance cannot be ignored when high-frequency currents pass through, especially noting that the bypass capacitor needs to pass through two vias when connecting the power layer and the ground layer, so the parasitic inductance of the via will increase exponentially. 3、 How to use vias? Through the analysis of the parasitic characteristics of vias above, we can see that in high-speed PCB design, seemingly simple vias often bring significant negative effects to circuit design. In order to reduce the adverse effects of parasitic effects on via holes, efforts can be made in the design to: 1. Consider both cost and signal quality, and choose a reasonable size of via hole. When necessary, different sizes of vias can be considered. For example, for power or ground vias, larger sizes can be considered to reduce impedance, while for signal routing, smaller vias can be used. Of course, as the via size decreases, the corresponding cost will also increase. The two formulas discussed above indicate that using thinner PCB boards is beneficial in reducing the two parasitic parameters of vias. 3. The signal routing on the PCB board should avoid changing layers as much as possible, that is to say, unnecessary vias should be avoided as much as possible. 4. The power and ground pins should be drilled with holes nearby, and the shorter the lead between the hole and the pin, the better. Multiple via holes can be considered in parallel to reduce equivalent inductance. 5. Place some grounding vias near the signal switching layer to provide a nearby circuit for the signal. Even some extra grounding vias can be placed on the PCB board.